Semiconductor integrated circuit

ABSTRACT

An electro static discharge protection element being formed by a diode including a well region of a first conductivity type on a surface of a semiconductor substrate, and a first diffusion layer of a second conductivity type in the well region. The first diffusion layer is surrounded by a second diffusion layer of the first conductivity type in the well region. The first diffusion layer has a surface on which a first contact region connected to an input/output terminal is formed. The first diffusion layer has a surface on which a second contact region connected to a reference voltage terminal is formed.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor integrated circuitdevice including an electro static discharge (ESD) protection element.

2. Description of the Prior Art

As the integration degree of a semiconductor integrated circuit deviceincreases along with the miniaturization and increase in density ofelements, the semiconductor integrated circuit device becomes moresusceptible to damages due to electro static discharge (hereinafterreferred to as “surge”). For example, the surge intruding via a pad forexternal connection destructs elements, such as an input circuit, anoutput circuit, an input/output circuit, and an internal circuit, whichincreases the possibility of reduced performance of elements. To copewith the problem, the semiconductor integrated circuit device includesan electro static discharge (ESD) protection element for protectionagainst the surge. The ESD protection element is provided between thepad for external connection and the input circuit, the output circuit,the input/output circuit, or the internal circuit.

FIG. 8A and FIG. 8B show a configuration of a conventional ESDprotection element, wherein FIG. 8A is a plan view, and FIG. 8B is across section taken along the line VIIIb-VIIIb of FIG. 8A (see, forexample, Japanese Laid-Open Patent Publication No. 2-58262).

In a well region 110 formed in a semiconductor substrate, a diffusionlayer 111 and a diffusion layer 112 are formed. The diffusion layer 111has a conductivity type opposite to that of the well region 110. Thediffusion layer 112 has the same conductivity type as that of the wellregion 110. The diffusion layer 111 and the diffusion layer 112 arearranged facing each other with a dielectric isolation region 113interposed therebetween. On the diffusion layers 111 and 112, aplurality of contact regions 114 and 115 are respectively formed. Thediffusion layers 111 and 112 are respectively connected to electrodes122 via plugs 121 formed in an interlayer dielectric film 120. Theelectrode 122 connected to the diffusion layer 111 is connected to a pad123 for external connection. The electrode 122 connected to thediffusion layer 112 is connected to a power source or a ground.

Upon intrusion of a surge via the pad 123 for external connection, adiode formed by the well region 110 and the diffusion layer 111 isbrought into conduction. As a result, the externally intruding surge isled to the power source or the ground connected to the diffusion layer112, making it possible to protect a circuit which is to be protected.

SUMMARY OF THE INVENTION

Along with the enhanced speed and multifunctionalization in personalcomputers, routers, and peripheral electronics devices in recent years,a high-speed interface having a transfer speed of an order of 1 GHz hasbeen required. However, if a protection element is formed for thehigh-speed interface, the protection element may influence a waveform oftransfer data. That is, when a signal is input to the high-speedinterface, a displacement current is induced by the protection element.In this case, the magnitude of the displacement current is proportionalto the product of capacitance of the protection element and thefrequency of the input signal. Therefore, if the frequency of the inputsignal increases, the influence on the waveform of the transfer data isno longer negligible.

To suppress the influence, it is necessary to reduce the capacitance ofthe protection element, and to reduce the capacitance of the protectionelement, it is necessary to reduce the area of the diffusion layer 111of the conventional protection diode of FIG. 8. However, if the area ofthe diffusion layer 111 is reduced, ability to discharge the surge isreduced, so that the primary function of protecting an element to beprotected can no longer be carried out. That is, there is a trade-offrelationship between reduced input capacitance and high resistance toESD. Therefore, it is not possible to realize an ESD element which isadapted to a high-speed interface and which has both characteristics ofthe reduced input capacitance and the high resistance to ESD.

In view of the above-mentioned problems, a main object of the presentinvention is to provide a semiconductor integrated circuit device whichhas a simple structure and which includes an electro static dischargeprotection element having reduced input capacitance and high resistanceto ESD.

To achieve the above-mentioned object, an electro static dischargeprotection element of the present invention has such a configurationthat a diffusion layer which constitutes a diode and which is formed ina well region is surrounded by a diffusion layer. The latter diffusionlayer having a conductivity type opposite to that of the formerdiffusion layer (the latter diffusion layer has the same conductivitytype as that of the well region). That is, a semiconductor integratedcircuit device of the present invention includes an electro staticdischarge protection element, the electro static discharge protectionelement being formed by a diode including: a well region of a firstconductivity type in a semiconductor substrate; and a first diffusionlayer of a second conductivity type in the well region, wherein thefirst diffusion layer is surrounded by a second diffusion layer of thefirst conductivity type in the well region, the first diffusion layerhas a surface on which a first contact region connected to aninput/output terminal is formed, and the second diffusion layer has asurface on which a second contact region connected to a referencevoltage terminal is formed.

According to such configuration, it is possible to increase the lengthalong which the first diffusion layer and the second diffusion layerface each other. Therefore, even in a case where a junction area of thefirst diffusion layer and the well region which constitute a diode isreduced, it is possible to discharge a surge current intruding into theinput/output terminal to the second diffusion layer surrounding thefirst diffusion layer. As a result, it is possible to realize asemiconductor integrated circuit device including an electro staticdischarge protection element having reduced input capacitance and highresistance to ESD.

Moreover, since the surge current is absorbed by the second diffusionlayer surrounding the first diffusion layer, it is possible to preventthe latch-up which occurs between the electro static dischargeprotection element and a CMOS circuit which is arranged in circumferenceof the electro static discharge protection element.

In a preferable embodiment, a dielectric isolation region is formedbetween the first diffusion layer and the second diffusion layer.According to the configuration, even in a case where the seconddiffusion layer is formed to surround the first diffusion layer, no PNjunction is formed between the first diffusion layer and the seconddiffusion layer. Therefore, it is possible to suppress an increase ininput capacitance of the electro static diffusion protection element.

In a preferable embodiment, the first diffusion layer is rectangular inshape, and the second contact region is formed only in a portion facinga long side of the first diffusion layer. Moreover, it is preferablethat the second contact region has end portions arranged in a positionin alignment with end portions of the first contact region formed alonga longitudinal direction of the first diffusion layer. According to theconfiguration, it is possible to prevent concentration of the surgecurrent on the end portions of the first contact region. Therefore, itis possible to realize a highly reliable electro static dischargeprotection element having reduced input capacitance and high resistanceto ESD.

In a preferable embodiment, the first diffusion layer is rectangular inshape, and the first contact region formed along a longitudinaldirection of the first diffusion layer has end portions which aregreater in area than the other portions of the first contact region.According to the configuration, it is possible to prevent concentrationof the surge current on the end portions of the first contact region.Therefore, it is possible to realize a highly reliable electro staticdischarge protection element having reduced input capacitance and highresistance to ESD.

In a preferable embodiment, the first diffusion layer is rectangular inshape, and a width of the second diffusion layer facing a short side ofthe first diffusion layer is narrower than a width of the seconddiffusion layer facing a long side of the first diffusion layer.According to the configuration, it is possible to shorten a path of thesurge current in the second diffusion layer. Therefore, it is possibleto realize a highly reliable electro static discharge protection elementhaving reduced input capacitance and high resistance to ESD.

In a preferable embodiment, the first diffusion layer is rectangular inshape, and a distance between the first diffusion layer and the seconddiffusion layer along a long side of the first diffusion layer isnarrower than a distance between the first diffusion layer and thesecond diffusion layer along a short side of the first diffusion layer.According to the configuration, it is possible to shorten a path of thesurge current in the second diffusion layer. Therefore, it is possibleto realize a highly reliable electro static discharge protection elementhaving reduced input capacitance and high resistance to ESD.

In a preferable embodiment, the first diffusion layer is formed into aplurality of divided diffusion regions, and the second diffusion layeris formed also between the divided diffusion regions. Moreover, it ispreferable that the divided diffusion regions are arranged at a regularinterval. According to the configuration, it is possible to increase alength along which the first diffusion layer and the second diffusionlayer face each other. Therefore, it is possible to realize an electrostatic discharge protection element which has further improvedresistance to ESD and reduced input capacitance.

According to the semiconductor integrated circuit device of the presentinvention, a length along which the first diffusion layer and the seconddiffusion layer face each other is increased, which makes it possible torealize a semiconductor integrated circuit device including an electrostatic discharge protection element having reduced input capacitance andhigh resistance to ESD.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a plan view illustrating a configuration of an electrostaticdischarge protection element of a semiconductor integrated circuitdevice of Embodiment 1 of the present invention, and FIG. 1B is a crosssection taken along the line Ib-Ib of FIG. 1A.

FIG. 2 is a plan view illustrating a configuration of an electrostaticdischarge protection element of a semiconductor integrated circuitdevice of Embodiment 2 of the present invention.

FIG. 3 is a plan view illustrating a configuration of an electrostaticdischarge protection element of a semiconductor integrated circuitdevice of Embodiment 3 of the present invention.

FIG. 4 is a plan view illustrating a configuration of an electrostaticdischarge protection element of a semiconductor integrated circuitdevice of Embodiment 4 of the present invention.

FIG. 5 is a plan view illustrating a configuration of an electrostaticdischarge protection element of a semiconductor integrated circuitdevice of Embodiment 5 of the present invention.

FIG. 6 is a plan view illustrating a configuration of an electrostaticdischarge protection element of a semiconductor integrated circuitdevice of Embodiment 6 of the present invention.

FIG. 7 is a plan view illustrating a configuration of an electro staticdischarge protection element according to a variation of Embodiment 6 ofthe present invention.

FIG. 8A is a plan view illustrating a configuration of a conventionalelectro static discharge protection element, and FIG. 8B is a crosssection taken along the line VIIIb-VIIIb of FIG. 8A.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will be described below withreference to the drawings. In the following drawings, components havingsubstantially the same function are indicated by the same referencenumerals for easy explanation. Note that, the present invention is notlimited to the embodiments below.

Embodiment 1

FIG. 1A and FIG. 1B are views illustrating a configuration of an electrostatic discharge protection element of a semiconductor integratedcircuit device of Embodiment 1 of the present invention, wherein FIG. 1Ais a plan view, and FIG. 1B is a cross section taken along the lineIb-Ib of FIG. 1A.

As shown in FIG. 1A and FIG. 1B, on a surface of a semiconductorsubstrate (not shown), an n-type well region 10 is formed which has, forexample, ions of n-type impurity implanted with a dose of 1E13 cm⁻².Further, in the well region 10, a p-type first diffusion layer 11 isformed which has, for example, ions of p-type impurity implanted with adose of 1E15 cm⁻². The well region 10 and the first diffusion layer 11constitute a diode, which is a protection element.

Moreover, a second diffusion layer 12 which is n type (the sameconductivity type as that of the well region 10) is formed in the wellregion 10 so as to surround the first diffusion layer 11, the seconddiffusion layer 12 having, for example, ions of an n-type impurityimplanted with a dose of 1E15 cm⁻². Between the first diffusion layer 11and the second diffusion layer 12, a dielectric isolation region 13formed by, for example, an oxide film is formed. Here, it is preferablethat the dielectric isolation region 13 is deeper than the firstdiffusion layer 11 and the second diffusion layer 12.

Furthermore, the first diffusion layer 11 has a surface on which firstcontact regions 14 are formed. The first contact regions 14 areconnected to an input/output terminal (pad for external connection) 23via contact plugs 21 formed in an interlayer dielectric film 20.Likewise, the second diffusion layer 12 has a surface on which contactregions 15 are formed. The second contact regions 15 are connected to areference voltage terminal (for example, a power source terminal or aground terminal) via contact plugs 21 formed in the interlayerdielectric film 20. Here, the first contact regions 14 and the secondcontact regions 15 are respectively formed into a plurality of dividedcontact regions. However, one continuing contact region which is notdivided may be formed. Alternatively, one contact region for each sideof the first diffusion layer 11 may be formed in the second diffusionlayer 12.

As described above, the second diffusion layer 12 are formed so as tosurround the first diffusion layer 11 constituting the diode, whichmakes it possible to increase the length along which the first diffusionlayer 11 and the second diffusion layer 12 face each other. Therefore,even in a case where a joint area of the first diffusion layer 11 andthe well region 10 is reduced, it is possible to discharge a surgecurrent intruding into the input/output terminal 23 to the seconddiffusion layer 12 surrounding the first diffusion layer 11. Therefore,even in a case where input capacitance of the protection element isreduced, ability to discharge the surge is not reduced. That is,adopting the configuration of the protection film as shown in FIG. 1Aand FIG. 1B makes it possible to realize an ESD protection element whichhas both characteristics of the reduced input capacitance and the highresistance to ESD.

As an example, in the configuration of the protection element shown inFIG. 1A and FIG. 1B, it is assumed that the n-type well region 10 hasphosphor (P) with a dose of 1.08E13 cm⁻², the p-type first diffusionlayer 11 has boron (B) with a dose of 4.4E15 cm⁻² and has a surface areaof 0.6×50 μm², and the n-type second diffusion layer 12 has arsenic (As)with a dose of 4.4E15 cm⁻² and has a surface area of 1.2×50 μm². In thiscase, the protection element has an input capacitance of about 0.1 pF.Moreover, even in a case where a surge which has a positive charge of2000 V is applied to the first diffusion layer 11, the protectionelement is not destructed, and the surge current is discharged to theground terminal via the second diffusion layer 12.

Also from the example mentioned above, it can be concluded that theprotection element of Embodiment 1 has sufficient performance withregard to the reduced input capacitance and the high resistance to thesurge to be applicable to a protection element for the high-speedinterface.

Moreover, since the surge current is absorbed by the second diffusionlayer 12 surrounding the first diffusion layer 11, it is possible tosuppress the transmission of the surge current to the CMOS transistorconstituting the semiconductor integrated circuit device. This makes itpossible to effectively prevent the latch-up of the CMOS transistor.

In Embodiment 1, the second diffusion layer 12 is formed so as tosurround the first diffusion layer 11. However, it is possible torealize the effects of the present invention of protecting the elementto be protected from the surge and preventing the latch-up even in acase where the first diffusion layer 11 is not completely surrounded bythe second diffusion layer 12.

Embodiment 2

FIG. 2 is a plan view illustrating a configuration of an electro staticdischarge protection element of a semiconductor integrated circuitdevice of Embodiment 2 of the present invention. The protection elementin FIG. 2 is different from the protection element of FIG. 1A and FIG.1B only in position of the contact regions 14 and 15. The firstdiffusion layer 11 and the second diffusion layer 12 in FIG. 2 have thesame configuration as that of FIG. 1A and FIG. 1B.

When the contact regions 14 and 15 are arranged as in FIG. 1A, a surgeintruding via the input/output terminal 23 may concentrate on a part ofcontact regions situated at both ends of a sequence of the contactregions 14 formed in the first diffusion layer 11, which may destructthe part of the contact regions. As a result, the resistance of theprotection element to the surge is reduced, which may reducereliability.

To prevent such concentration of the surge current, a protection elementof Embodiment 2 has such a configuration that the second contact regions15 are formed only in portions facing the long sides of the firstdiffusion layer 11 as shown in FIG. 2. According to the configuration,the surge current intruding into the first diffusion layer 11 flows tothe contact regions 15 in two directions, the contact regions 15 beingformed in portions of the second diffusion layer 12 facing the longsides of the first diffusion layer 11. Then, the surge current isdischarged to a power supply terminal or to a ground. Therefore, it ispossible to prevent the concentration of the surge current on the firstcontact regions situated at the both ends of a sequence of the firstcontact regions 14. Therefore, it is possible to realize a highlyreliable electro static discharge protection element having reducedinput capacitance and high resistance to ESD.

In order to effectively prevent the concentration of the surge current,it is preferable that second contact regions 15 a situated at both endsof a sequence of the second contact regions 15 are arranged in alignmentwith first contact regions 14 a situated at both ends of a sequence ofthe first contact regions 14 formed along a longitudinal direction ofthe first diffusion layer 11 as shown in FIG. 2. Moreover, the firstcontact regions 14 and the second contact regions 15 are formed into aplurality of divided contact regions. However, instead of the dividedcontact regions, one continuing contact region may be formed.

Embodiment 3

FIG. 3 is a plan view illustrating a configuration of an electro staticdischarge protection element of a semiconductor integrated circuitdevice of Embodiment 3 of the present invention. The protection elementin FIG. 3 is different from the protection element of FIG. 1A and FIG.1B only in position of the contact regions 14 and 15. The firstdiffusion layer 11 and the second diffusion layer 12 in FIG. 3 have thesame configuration as that of FIG. 1A and FIG. 1B.

In the protection element of Embodiment 3, reduction in resistance tothe surge is prevented even in a case where a surge current concentrateson first contact regions situated at both ends of a sequence of thefirst contact regions 14. The protection element of Embodiment 3 hassuch a configuration that first contact regions 14 b situated at bothends of a sequence of the first contact regions 14 formed along alongitudinal direction of the first diffusion layer 11 are greater inarea than each of the first contact regions 14 as shown in FIG. 3.According to the configuration, even in a case where the surge currentconcentrates on the first contact regions 14 b on the both ends of thesequence of the first contact regions 14, it is possible to prevent thedestruction of the contact region, because the first contact regions 14b are greater in area than the first contact regions 14. Therefore, itis possible to realize a highly reliable electro static dischargeprotection element having the reduced input capacitance and highresistance to ESD.

In a case where the first contact regions 14 are formed into a pluralityof divided contact regions as shown in FIG. 3, the first contact regions14 b on end portions of the first diffusion layer 11 are formed to havea greater area than that of the contact regions 14 which are formed intodivided contact regions. Moreover, in a case where one continuingcontact region is formed instead of divided contact regions, both endportions of the contact region are formed to have a greater area thanthat of the other portions of the contact region. Moreover, instead ofincreasing the area, the number of contact regions on the end portionsof the first diffusion layer 11 may be increased, the contact regionshaving the same size.

Embodiment 4

FIG. 4 is a plan view illustrating a configuration of an electro staticdischarge protection element of a semiconductor integrated circuitdevice of Embodiment 4 of the present invention. The electro staticdischarge protection element in FIG. 4 is different from the electrostatic discharge protection element of FIG. 1A and FIG. 1B only in shapeof the second diffusion layer 12. Other components in FIG. 4 have thesame configuration as that of FIG. 1A and FIG. 1B.

As shown in FIG. 2, forming the second contact regions 15 only inportions facing the long sides of the first diffusion layer 11 makes itpossible to prevent the concentration of a surge current on both ends ofa sequence of the first contact regions 14. However, in a salicideprocess, a part of the surge current intruding into the first diffusionlayer 11 flows to the contact regions 15 via the second diffusion layer12 facing the short sides of the first diffusion layer 11 due to a lowresistance of the diffusion layer. Therefore, the surge current mayconcentrate on the both ends of a sequence of the first contact regions14.

A protection element of Embodiment 4 prevents the concentration of thesurge current on the both ends of a sequence of the first contactregions 14. The protection element of Embodiment 4 has such aconfiguration that the width W1 of the second diffusion layer 12 facingthe short sides of the first diffusion layer 11 is formed to be narrowerthan the width W2 of the second diffusion layer 12 facing the long sidesof the first diffusion layer 11 as shown in FIG. 4. According to theconfiguration, it is possible to reduce the surge current which flows tothe contact regions 15 via the second diffusion layer 12 facing theshort sides of the first diffusion layer 11 and to prevent theconcentration of the surge current on the both ends of a sequence of thefirst contact regions 14.

Embodiment 5

FIG. 5 is a plan view illustrating a configuration of an electro staticdischarge protection element of a semiconductor integrated circuitdevice of Embodiment 5 of the present invention. The electro staticdischarge protection element in FIG. 5 is different from the electrostatic discharge protection element of FIG. 4 only in shape of thedielectric isolation region 13. Other components in FIG. 5 have the sameconfiguration as that of FIG. 4.

According to the configuration as shown in FIG. 4, the width W1 of thesecond diffusion layer 12 facing the short sides of the first diffusionlayer 11 is formed to be narrower than the width W2 of the seconddiffusion layer 12 facing the long sides of the first diffusion layer11, which shortens a path of the surge current in the second diffusionlayer. Therefore, it is possible to prevent the concentration of thesurge current on the both ends of the first contact regions 14. However,it is not possible to completely prevent that a part of the surgecurrent flows to the second diffusion layer 12 facing the short sides ofthe first diffusion layer 11.

In order to further reduce the surge current flowing to the seconddiffusion layer 12 facing the short sides of the first diffusion layer11, a protection element of Embodiment 5 has such a configuration thatthe distance D1 between the first diffusion layer 11 and the seconddiffusion layer 12 along the long sides of the first diffusion layer 11is formed to be narrower than the distance D2 between the firstdiffusion layer 11 and the second diffusion layer 12 along the shortsides of the first diffusion layer 11. According to the configuration,it is possible to further reduce the surge current flowing to the seconddiffusion layer 12 facing the short sides of the first diffusion layer11.

Embodiment 6

FIG. 6 is a plan view illustrating a configuration of an electro staticdischarge protection element of a semiconductor integrated circuitdevice of Embodiment 6 of the present invention and has such aconfiguration that the first diffusion layer 11 of the protectionelement of FIG. 1 is formed into a plurality of divided diffusionregions 11 a. In this case, the second diffusion layer 12 is formed alsoin part 12 a between the divided diffusion regions.

According to the configuration, it is possible to further increase thelength along which each of the first diffusion layer 11 a and the seconddiffusion layer 12 and 12 a face each other. Therefore, it is possibleto realize an electro static discharge protection element having furtherimproved resistance to ESD and reduced input capacitance.

In Embodiment 6, various methods may be adopted to divide the firstdiffusion layer 11 into a plurality of diffusion regions 11 a. Thedivided diffusion regions 11 a may be square or rectangular in shape.Alternatively, the diffusion regions 11 a may be polygonal as shown inFIG. 7. Moreover, the arrangement of the divided diffusion regions 11 ais not limited to one line as shown in FIG. 6 and FIG. 7. The diffusionregions 11 a may be arranged in several lines. Note that, it ispreferable that the divided diffusion regions 11 a are arranged at aregular interval to obtain a uniform path for the surge current.

The present invention has been described with reference to the preferredembodiments. However, these descriptions are not to limit the scope ofthe invention, and of course, various modifications are possible. Forexample, in the above-mentioned embodiments, the well region 10 is ntype, the first diffusion layer 11 is p type, and the second diffusionlayer 12 is n type. However, the opposed conductivity type may be used.Although the first diffusion layer 11 in embodiments is rectangular inshape, only both end portions along the long sides may have a greaterarea. Also in this case, it is possible to prevent the concentration ofthe surge current on the both end portions.

1. A semiconductor integrated circuit device comprising an electrostatic discharge protection element, the electro static dischargeprotection element being formed by a diode including: a well region of afirst conductivity type in a semiconductor substrate; and a firstdiffusion layer of a second conductivity type in the well region,wherein the first diffusion layer is surrounded by a second diffusionlayer of the first conductivity type in the well region, the firstdiffusion layer has a surface on which a first contact region connectedto an input/output terminal is formed, and the second diffusion layerhas a surface on which a second contact region connected to a referencevoltage terminal is formed.
 2. The semiconductor integrated circuitdevice of claim 1, wherein a dielectric isolation region is formedbetween the first diffusion layer and the second diffusion layer.
 3. Thesemiconductor integrated circuit device of claim 1, wherein the firstdiffusion layer is rectangular in shape, and the second contact regionis formed only in a portion facing a long side of the first diffusionlayer.
 4. The semiconductor integrated circuit device of claim 3,wherein the second contact region has end portions arranged in aposition in alignment with end portions of the first contact regionformed along a longitudinal direction of the first diffusion layer. 5.The semiconductor integrated circuit device of claim 1, wherein thefirst diffusion layer is rectangular in shape, and the first contactregion formed along a longitudinal direction of the first diffusionlayer has end portions which are greater in area than the other portionsof the first contact region.
 6. The semiconductor integrated circuitdevice of claim 1, wherein the first diffusion layer is rectangular inshape, and a width of the second diffusion layer facing a short side ofthe first diffusion layer is narrower than a width of the seconddiffusion layer facing a long side of the first diffusion layer.
 7. Thesemiconductor integrated circuit device of claim 1, wherein the firstdiffusion layer is rectangular in shape, and a distance between thefirst diffusion layer and the second diffusion layer along a long sideof the first diffusion layer is narrower than a distance between thefirst diffusion layer and the second diffusion layer along a short sideof the first diffusion layer.
 8. The semiconductor integrated circuitdevice of claim 1, wherein the first diffusion layer is formed into aplurality of divided diffusion regions, and the second diffusion layeris formed also between the divided diffusion regions.
 9. Thesemiconductor integrated circuit device of claim 8, wherein the divideddiffusion regions are arranged at a regular interval.
 10. Thesemiconductor integrated circuit device of claim 1, wherein the firstcontact region and the second contact region are respectively formedinto a plurality of divided contact regions.